Rocketchip
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cpe:2.3:a:chipsalliance:rocketchip:*:*:*:*:*:*:*:*
part: a version: * update: *
| Vendor | Chipsalliance (b26d6fed-9305-5685-bc07-a6351181a7e2) |
|---|---|
| Product | Rocketchip (1ebe3693-0cfa-52b0-bd87-88d038af1809) |
| Edition | * |
| Language | * |
| Software edition | * |
| Target software | * |
| Target hardware | * |
| Other | * |
| Notes | Imported from purl2cpe mapping |
PURL mappings
| PURL | Source | Last updated |
|---|---|---|
pkg:github/chipsalliance/rocket-chip |
purl2cpe | 2026-06-01 10:16:36.066293 |
Vulnerability references
| Identifier | cpeApplicability | Submitted | db.gcve.eu details | Rationale |
|---|---|---|---|---|
CVE:CVE-2025-63384 |
vulnerable | 2026-06-08 07:39:17.549575 |
Details available
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.
Published: 2025-11-10T00:00:00.000Z
Updated: 2025-11-12T20:39:11.448Z |
Imported from gcve-enriched-dumps CVE data |
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