Intel(R) Xeon(R) 6 Processors When Using Intel(R) Tdx
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cpe:2.3:a:n/a:intel(r)_xeon(r)_6_processors_when_using_intel(r)_tdx:*:*:*:*:*:*:*:*
part: a version: * update: *
| Vendor | N/A (22f567d3-1203-528c-8f0e-3eb9c2f6ca78) |
|---|---|
| Product | Intel(R) Xeon(R) 6 Processors When Using Intel(R) Tdx (24396eb6-266d-5c8f-8f69-1273652363b2) |
| Edition | * |
| Language | * |
| Software edition | * |
| Target software | * |
| Target hardware | * |
| Other | * |
| Notes | Imported from gcve-enriched-dumps CVE data |
PURL mappings
| PURL | Source | Last updated |
|---|---|---|
| No PURL mappings for this CPE yet. | ||
Vulnerability references
| Identifier | cpeApplicability | Submitted | db.gcve.eu details | Rationale |
|---|---|---|---|---|
CVE:CVE-2025-31936 |
vulnerable | 2026-09-16 04:26:45.886766 |
Details available
Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6 processors when using Intel(R) TDX within SMM may allow an escalation of privilege. SMM adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (high), integrity (high) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (none), integrity (none) and availability (none) impacts.
Published: 2026-08-11T16:28:06.168Z
Updated: 2026-08-12T14:46:56.476Z |
Imported from gcve-enriched-dumps CVE data |
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